1. Field of the Invention
The present invention relates to a method and an apparatus for controlling a phase-locked loop (PLL) system to generate a synchronized output signal during periods when the incoming reference signal is interrupted, and more particularly to a new method and apparatus for an all digital holdover circuit.
2. Description of the Related Art
In data transmission systems, the transmitter and the receiver must be synchronized to accurately access transmitted data. Phased-locked loop (PLL) circuits have been used for many years to achieve such synchronization. A typical PLL circuit receives an accurate reference input signal and performs a feedback control operation to lock the output signal in phase with the incoming reference signal. Essentially, an analog PLL circuit continuously tests the output of a voltage-controlled oscillator (VCO) through a feedback loop, and when the output of the VCO drifts away from the incoming reference signal, an error voltage is generated to pull the VCO back into synchronization with the incoming reference signal. PLL circuits thus have been widely used in a variety of applications such as communication systems, computers networks, television transmissions, etc.
As illustrated in FIG. 1, a conventional analog PLL circuit consists of three main components: a phase detector (PD) 14, a loop filter 12, and a voltage controlled oscillator (VCO) 10. The conventional analog PLL circuit illustrated in FIG. 1 further includes a frequency divider 16 which adjusts the frequency of the VCO output signal f.sub.out to correspond to the frequency of an incoming reference signal. The PD 14 compares an incoming reference signal f.sub.ref and the fed-back output of VCO 10 f.sub.out /N, and generates an error signal which represents any phase differences between the reference signal f.sub.ref and the VCO output. The loop filter 12 acts as a low-pass filter, thereby removing alternating current (ac) components to provide a direct-current (dc) voltage signal to drive the VCO 10. This input voltage supplied from the loop filter 12 controls the output frequency of the VCO. The output f.sub.out of the VCO 10 is fed-back to the PD 14 through the frequency divider 16 and is continuously driven in a direction that will minimize the error signal generated by the PD 14. Once the signals f.sub.ref and f.sub.out /N are made equal, the output of VCO is said to be locked to the input reference signal, and any phase differences between the two signals will be controlled.
All digital PLLs have also been developed to continuously monitor the output of a digital control oscillator (DCO), instead of the analog VCO, and to generate digital control signals which pull the DCO back into synchronization with the incoming reference signal. Such all digital PLLs generally provide advantages over analog PLLs because expensive external components, such as a VCxO, are not required.
A problem occurs for conventional analog/digital PLL circuits used to synchronously read a transmitted information stream when the incoming reference signal is lost or interrupted. During the absence of the incoming reference signal, the output frequency of the VCO/DCO may drift, thereby causing the receiver to read data from the received information stream out of synchronization. Prior art techniques have therefore been developed to compensate for periods when the incoming reference signal is interrupted.
One such prior art technique for generating an in-phase output signal during a period of incoming reference signal absence selects an alternate reference signal when the primary incoming reference signal is lost. This holdover system, however, is not applicable to communication systems which use a single reference signal.
In another prior art holdover technique, two PLL circuits, each utilizing a VCxO, are provided to protect the accuracy of the output signal of the first PLL when the incoming signal is absent. In this system, however, two separate PLL circuits are required, in addition to a digital-to-analog converter which is needed to convert the signals from a digital up/down counter of the second PLL circuit to the analog signal needed for VCO input.
In yet another prior art technique, a PLL circuit having a VCO employs a crystal maintained at a constant temperature so that a phase-locked lock signal having minimal drift is provided. In this analog system, however, high power consumption is required to maintain the crystal at the constant temperature.